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Page viii 4.8 Miscellaneous Effects 251 4.8.1 Store in Instruction Stream Delay 251 4.9 Conclusions 259 4.10 Some Areas for Further Research 260 4.11 Data Notes 260 4.12 Annotated Bibliography 261 4.13 Problem Set 262 5 Cache Memory 265 5.1 Introduction 265 5.2 Basic Notions 266 5.3 Cache Organization 269 5.4 Cache Data 274 5.5 Adjusting the Data for Cache Organization 277 5.6 Write Policies 280 5.7 Strategies for Line Replacement at Miss Time 283 5.7.1 Fetching a Line 284 5.7.2 Line Replacement 286 5.8 Cache Environment 287 5.9 Other Types of Cache 291 5.10 Split I- and D-Caches 294 5.10.1 I- and D-Caches 294 5.10.2 Code Density Effects 297 5.11 On-Chip Caches 299 5.12 Two-Level Caches 302 5.12.1 Logical Inclusion 308 5.13 Write Assembly Cache 309 5.14 Cache References per Instruction 311 5.14.1 Instruction Traffic 311 5.14.2 Data Traffic 314 5.15 Technology-Dependent Cache Considerations 317 5.16 Virtual-to-Real Translation 322 5.16.1 Translation Lookaside Buffer (TLB) 323 5.17 Overlapping the T cycle in V ® R Translation 325 5.17.1 Set Associative Caches 326 5.17.2 Virtual Caches 327 5.17.3 Real Caches Using Colored Pages 328 5.18 Studies 329 5.18.1 Actual Reference Traffic 331 5.19 Design Summary 336
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