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Page ix 5.19.1 Cache Evaluation Design Rules 336 5.19.2 Cache/TLB Excess CPI Design Rules 337 5.20 Conclusions 337 5.21 Some Areas for Further Research 338 5.22 Data Notes 338 5.23 Bibliography 340 5.24 Problem Set 341 6 Memory System Design 345 6.1 Introduction 345 6.2 The Physical Memory 349 6.2.1 The Memory Module 350 6.2.2 Error Detection and Correction 354 6.2.3 Memory Buffers 358 6.2.4 Partitioning of the Address Space 358 6.3 Models of Simple Processor-Memory Interaction 360 6.3.1 Memory Systems Design 361 6.3.2 Multiple Simple Processors 362 6.3.3 Hellerman's Model 363 6.3.4 Strecker's Model 363 6.3.5 Rau's Model 365 6.4 Processor-Memory Modeling Using Queueing Theory 365 6.4.1 Performance Models of Processor Memory Interactions 368 6.4.2 Arrival Distribution 369 6.4.3 Service Distribution 370 6.4.4 Terminology 371 6.4.5 Queue Properties 372 6.5 Open-, Closed-, and Mixed-Queue Models 374 6.5.1 The Open-Queue (Flores) Memory Model 376 6.5.2 Closed Queues 378 6.5.3 Mixed Queues 382 6.6 Waiting Time, Performance, and Buffer Size 384 6.6.1 Pipelined Processors 385 6.6.2 Designing a M/M/1 Buffer Given a Mean Queue Size 389 6.6.3 Comparison of Memory Models 391 6.7 Review and Selection of Queueing Models 394 6.8 Processors with Cache 396 6.8.1 Fully and Partially Blocking Caches 397 6.8.2 Accessing a Line (Tline access) 397 6.8.3 Contention Time (Tbusy) and Copyback Caches 400
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