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3.4 Breaks in Machine Execution |
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3.4.1 Instruction Run Length |
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3.4.2 Branches |
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3.4.3 Branch Target Distribution |
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3.4.4 Condition Code Testing |
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3.4.5 Move and Arithmetic Class Operations |
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3.4.6 Register-Based Addressing |
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3.4.7 Decimal and Character Operand Length |
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3.5 Conclusions |
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3.6 Some Areas for Further Research |
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3.7 Data Notes |
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3.8 Annotated Bibliography |
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3.9 Problem Set |
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4
Pipelined Processor Design |
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4.1 Introduction |
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4.1.1 Evolution of a Computer Processor Family |
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4.1.2 Processor Design |
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4.1.3 Organization of the Chapter |
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4.2 Approaching Pipelined Processors |
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4.2.1 Examples of Pipeline Implementations |
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4.3 Evaluating Pipelined Processor Performance |
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4.4 Design of a Pipelined Processor |
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4.4.1 Cache Access Controller |
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4.4.2 Accounting for the Effect of Buffers in a Pipelined System |
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4.4.3 Buffer Design |
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4.4.4 Designing a Buffer for a Mean Request Rate |
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4.4.5 I-Buffers Designed for Maximum Request Rates |
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4.5 Branches |
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4.5.1 Branch Elimination |
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4.5.2 Branch Speedup |
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4.5.3 Branch Prediction Strategies |
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4.5.4 Branch Target Capture: Branch Target Buffers |
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4.6 Interlocks |
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4.6.1 Decoder and Interlocks |
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4.6.2 Bypassing |
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4.6.3 Address Generation Interlocks |
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4.6.4 Execution Interlocks and Interlock Tables |
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4.7 Run-On Delay |
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