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Page vi 2 Time, Area, and Instruction Sets 63 2.1 Introduction 63 2.2 Time 64 2.2.1 The Nature of a Cycle 64 2.2.2 Partitioning Instruction Execution into Cycles 65 2.2.3 Clocking Overhead and Reliable Clocking 66 2.2.4 Pipelined Processors 70 2.2.5 Optimum Pipelining 70 2.2.6 Cycle Quantization 77 2.2.7 Wave Pipelining 79 2.3 Cost-Area 83 2.3.1 Area 84 2.3.2 Data Storage 93 2.4 Technology State of the Art 99 2.5 The Economics of a Processor Project: A Study 103 2.5.1 Phase 1: Development 106 2.5.2 Phase 2: Early Manufacturing 106 2.5.3 Phase 3: Production 107 2.5.4 Phase 4: All Good Things Must Come to an End 108 2.6 Instruction Sets: Processor Evaluation Metrics 109 2.6.1 Program Execution 110 2.6.2 Instruction Set Comparisons 112 2.6.3 Invariant Effects 117 2.6.4 Code Density 118 2.6.5 Role of Registers, Evaluation Stacks, and Data Buffers 124 2.7 Conclusions 132 2.8 Some Areas for Further Research 133 2.9 Data Notes 134 2.10 Annotated Bibliography 134 2.11 Problem Set 136 3 Data: How Programs Behave 141 3.1 Introduction 141 3.2 Instruction Usage 142 3.2.1 Data Categories 142 3.2.2 Format Distribution 144 3.2.3 Operation Set Distribution 144 3.3 Process Management 150 3.3.1 Procedure Calls: User State 150 3.3.2 Calls to the System 153
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