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Figure 2.26
Net die area. |
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defect density of one defect per square centimeter; for economic reasons, we target an initial yield of 10%. |
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Y = e-rDA, |
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where rD = 1 defect/cm2, Y = 0.1. Then |
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In other words, the gross chip area available to us is 230 mm2. This is the total die area of the chip, but such things as pads for the wire bonds that connect the chip to the external world, drivers for these connections, and power supply lines all act to decrease the amount of chip area available to the designer. In general, we allow 20% of the chip areausually around the periphery of the chipto accommodate these functions: |
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Pads + Guard Ring + Pad Drivers + Power Supply |
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= 20% of 230 mm2 = 46mm2. |
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Hence, the net area is 184 mm2. This is the net area available to the microprocessor designer. |
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Feature Size The smaller the feature size, the more logic that can be accommodated within a fixed area. As we discussed earlier, the rbe has been empirically determined to be approximately 2700 l2. Assume we have a process whose minimum feature size is one micron. Therefore, |
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f = 1m |
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f = 2l, |
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