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Figure 2.25
Area of on-chip data memory (cache and register
file) as a function of memory capacity. |
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To illustrate the usefulness of the area model, consider a tradeoff between register area and cache area [207]. Figure 2.25 shows a crossover point at about 128 words. Below this point, three-ported registers occupy less area per word, while beyond 128 words (512 bytes) a cache, depending on its organization, occupies less area per word (or bit or byte). |
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The rbe model is a simplification. It generally matches the observed area (mean error 9% [207]) occupied by actual designs. For example, the rbe model is susceptible to error because it does not model several parameters such as the aspect ratiothe ratio of height to width of a particular storage unit. |
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Study 2.3 A Baseline Microprocessor Area Model |
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The key to efficient microprocessor design is chip floor planning. The process of chip floor planning is not much different from the process of floor-planning a residence. Each functional area of the processor must be allocated sufficient room for its implementation. Functional units that frequently communicate must be placed close together. Sufficient room must be allocated for connection paths. |
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To illustrate possible tradeoffs that can be made in optimizing the chip floor plan, we introduce in this section a baseline microprocessor with designated areas for various functions. The area model is based upon empirical observations made of existing chips, design experience, and, in some cases, logical deduction (e.g., the relationship between a floating-point adder and an integer ALU). The processor described here ought not to be considered optimal in any particular sense, but rather a typical example of a number of microprocessors in the marketplace today. |
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The Starting Point The microprocessor design process begins with an understanding of the parameters of the semiconductor process. Suppose we expect to be able to use a manufacturing process that has or will have a |
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