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The integer registers are assumed to be 32 registers by 32 bits and three-ported. This means that the integer register set occupies |
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38 ´ 38 = 1,444 rbe, |
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1,444 rbe ´ 675m2/rbe = 0.97mm2. |
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At this point, we define a unit of area (A) equal to f2´ 106 (f in microns) or 1mm2 with f = 1. This corresponds to 1,481 rbe. Thus, our three-ported register set occupies 0.97mm2 or .'A, which we round to 1A. Empirically, it has been determined that the integer ALU for 32-bit operands occupies about the same area as a 32 ´ 32-bit register set, so the integer ALU occupies 1A. |
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The Architecture Most instruction sets have basically the same operand vocabulary (excepting very early RISC machines, which accommodated very few operations, or some mainframe architectures (especially VAX) that accommodated a very large number of operations and variants). For our baseline, we select a modern (early 1990s) type of microprocessor: a load/store (L/S) architecture with 32 registers, each of 32 bits, with an integrated floating-point unit and corresponding instruction set. The floating-point unit is expected to be accommodated on-chip. In the style of familiar microprocessors, our baseline will be pipelined with a short pipeline, such as four or five stages, which will serve to minimize the delays due to branches. The instruction set affects the total available area only slightly. Its primary influence is through the area required for the register set. The decoder itself is allocated 1A; a more or less elaborate decoder will not greatly affect the total amount of area available to the designer. Any of the following paths: |
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may determine the cycle time. Ideally, the designer works to achieve the situation where perhaps several of the preceding simultaneously limit cycle time. |
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An Area Model The following is a breakdown of the area required for various functional units used in the baseline processor. |
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