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| Table 2.2 Summary of relative areas. |
| | Item Size in rbe | | | 1 register bit (rbe) | 1.0 rbe | | 1 static RAM bit as used in an on-chip cache | 0.6 rbe | | 1 CAM bit as used in a fully associative cache directory | 2.0 rbe | | 1 DRAM bit as used in a large DRAM array | 0.1 rbe | | rbe corresponds to: | | | in feature size, f | 1 rbe = 675f2 | | in resolution, l | 1 rbe = 2700l2 | | Item | Size in A Units | | A corresponds to 1 mm2 with f = 1m. | | | 1A | = f2´ 106(f in microns) | | 1A | = 1481 rbe |  |
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A ''3-ported" register (2 read-1 write, 32 ´ 32b) is (32 + 6) * (32 + 6)
= 1444 rbe |
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| » 1A (= 0.975A) | | A 4KB direct mapped cache with 16B lines and 24b tag (directory entry) would have: | | | Data bits | = 4096 ´ 8 = 32,768 | | Tag bits |  | | Cache size | = 195 + .6[32,768 + 6,144] | | = 23,542 rbe | | Total | = 15.9A |
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is referenced to a six-transistor static cell with high bandwidtha register bit isolated from its input/output circuitry. A six-transistor static cell with lower bandwidth would use less area and a DRAM-bit cell would use still less. Empirically, they would have the relationship shown in Table 2.2. |
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Static RAM cells are used to reduce the area of on-chip caches at the expense of bandwidth and access time. In this book, all on-chip storage (cache, buffers, etc.)exclusive of registers themselves is assumed to be static cells unless otherwise noted. Other choices such as "fast" DRAM, etc., can readily be scaled. |
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