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Figure 2.22
Device with registration uncertainty. |
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Figure 2.23
Registration uncertainty for a device. |
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The minimum size for a diffusion region would be 2l with a necessary allowance of 3l between adjacent diffusion regions. Thus, a single transistor is 4l2, positioned in a minimum region of 25l2. |
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If we start with a device 2l´ 2l (Figure 2.22), then a device of nominal 2l´ 2l can extend to 4l´ 4l (Figure 2.23). Then we need at least 1l isolation from any other device or 25l2 for the overall device area. |
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For us, the minimum feature size (f) is the length of one polysilicon gate, or the length of one transistor, f = 2l. Clearly, we could define our design in terms of l2, as in the preceding, and any other processor feature (gate, register size, etc.) can be expressed as a number of transistors (plus interstitial area, other componentry, etc.). Thus, the selection of the area unit is arbitrary to a point. However, we would like to choose a unit that represents primary architectural tradeoffs. While an ALU bit is probably as reasonable as any arbitrary measure of area, adders and data paths are usually fixed portions of a processor design; moreover, areas such as register size, cache size, and TLB size are areas where the designer has more discretion. Thus, for our purposes, we have selected the register bit equivalent (rbe) as being the basic area measure. In practical designs, the six-transistor register cell represents about 2700l2. This is significantly more than six times the area of a single transistor, since it includes other components, connections, and necessary inter-bit isolating spaces. |
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One rbe equals the area of a bit storage cell. Even in the context of a MOS-based VLSI technology, there is no universal bit storage cell. Our unit rbe |
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