|
|
 |
|
|
|
|
[232] G. Pfister, W. Brantley, D. George, S. Harvey, W. Kleinfelder, K. McAuliffe, E. Melton, V. Norton, and J. Weiss. The IBM Research parallel processor prototype (RP3): Introduction and architecture. In Proceedings of the International Conference on Parallel Processing, pages 764789. IEEE, August 1985. |
|
|
|
 |
|
|
|
|
[233] G. F. Pfister and V. A. Norton. ''Hot spot" contention and combining in multistage interconnection networks. IEEE Transactions on Computers, pages 943948, October 1985. |
|
|
|
 |
|
|
|
|
[234] T. M. Pinkston. The GLORI Strategy for Multiprocessors: Integrating Optics into the Interconnect Architecture. PhD thesis, Stanford University, December 1992. CSL-TR-92-552. |
|
|
|
 |
|
|
|
|
[235] C. Polychronopoulos, M. Girkar, M. Haghighat, C. L. Lee, B. Leung, and D. Schouten. Parafrase-2: An environment for parallelizing, partitioning, synchronizing, and scheduling programs on multiprocessors. In Proceedings of the 1989 International Conference on Parallel Processing, pages 3948, 1989. Volume 2 of 3. |
|
|
|
 |
|
|
|
|
[236] J. Protic, M. Tomasevic, and V. Milutinovic. A survey of distributed shared memory systems. In Proceedings of the Hawaii International Conference on System Sciences, Maui, Hawaii, January 1995. |
|
|
|
 |
|
|
|
|
[237] S. Przybylski, M. Horowitz, and J. Hennessy. Characteristics of performance-optimal multi-level cache hierarchies. In Proceedings of the 16th Annual Symposium on Computer Architecture, pages 114121, June 1989. |
|
|
|
 |
|
|
|
|
[238] S. A. Przybylski. New DRAM Technologies. MicroDesign Resources, ?, 1994. |
|
|
|
 |
|
|
|
|
[239] G. Radin. The 801 minicomputer. In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 3947, Palo Alto, CA, March 1982. |
|
|
|
 |
|
|
|
|
[240] M. R. Ransford. MC 68040 cache design study. NCR Journal, 3(2), December 1989. |
|
|
|
 |
|
|
|
|
[241] B. R. Rau. Program Behavior and the Performance of Memory Systems. PhD thesis, Stanford University, July 1977. |
|
|
|
 |
|
|
|
|
[242] B. R. Rau, D. Yen, W. Yen, and R. Towle. The CYDRA 5 departmental supercomputer. IEEE Computer, 22:1235, January 1989. |
|
|
|
 |
|
|
|
|
[243] C. V. Ravi. On the bandwidth and interference in interleaved memory systems. IEEE Transactions on Computers, C-21:899901, August 1972. |
|
|
|
 |
|
|
|
|
[244] A. L. N. Reddy and P. Banerjee. An evaluation of multiple-disk I/O systems. IEEE Transactions on Computers, 38(12):16801690, December 1989. |
|
|
|
 |
|
|
|
|
[245] K. J. Richardson and M. J. Flynn. TIME: Tools for input/output and memory evaluation. In V. Milutinovic, editor, 25th Hawaii International Conference on System Sciences, pages 5866. IEEE, January 1992. |
|
|
|
 |
|
|
|
|
[246] E. M. Riseman and C. C. Foster. The inhibition of potential parallelism. IEEE Transactions on Computers, C-21:14051411, December 1972. |
|
|
|
 |
|
|
|
|
[247] G. Rossmann and B. Rau. System/360 program statistics. Internal Report, Palyn Associates, San Jose, CA, January 1974. |
|
|
|
 |
|
|
|
|
[248] G. E. Rossmann. Personal communication. |
|
|
|
 |
|
|
|
|
[249] R. M. Russell. The CRAY-1 computer system. Communications of the ACM, 21(1):6372, January 1978. |
|
|
|
 |
|
|
|
|
[250] James W. Rymarczyk. Coding guidelines for pipelined processors. In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 1219. ACM, March 1982. |
|
|
|
|
|