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Page 759 Table F.7 Berkeley CPU actions. State Read Hit Write Hit Read Miss Write Miss Invalid N/A N/A Issue bus read. Next state = Valid. Issue bus write miss. Write data to cache. Next state = Dirty. Valid Supply data to processor. Next state = Valid. Issue bus invalidation. Write data. Next state = Dirty. Issue bus read. Next state = Valid. Issue bus write miss. Write data to cache. Next state = Dirty. Shared-Dirty Supply data to processor. Next state = Shared-Dirty. Issue bus invalidation. Write data. Next state = Dirty. Write old line to memory. Issue bus read. Next state = Valid. Write old line to memory. Issue bus write miss. Write data to cache. Next state = Dirty. Dirty Supply data to processor. Next state = Dirty. Write, no delay. Next state = Dirty. Write old line to memory. Issue bus read. Next state = Valid. Write old line to memory. Issue bus write miss. Write data to cache. Next state = Dirty. Table F.8 Berkeley bus actions. State Bus Read Bus Write Miss Bus Invalidation Invalid No Action No Action No Action Valid No Action. Next state = Invalid Next state = Invalid Shared-Dirty Supply data. Next state = Shared-Dirty Supply data. Next state = Invalid Next state = Invalid Dirty Supply data. Next state = Shared-Dirty Supply data. Next state = Invalid N/A
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