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Page 758 Table F.5 Illinois CPU actions. State Read Hit Write Hit Read Miss Write Miss Invalid N/A N/A Issue bus read. If data is from memory, next state = Valid-Exclusive; otherwise next state = Shared. Issue bus write miss. Write data to cache. Next state = Dirty. Valid-Exclusive Supply data to processor. Next state = Valid-Exclusive. Write, no delay. Next state = Dirty. Issue bus read. If data is from memory, next state = Valid-Exclusive; otherwise next state = Shared. Issue bus write miss. Write data to cache. Next state = Dirty. Shared Supply data to processor. Next state = Shared. Issue bus invalidation. Write data. Next state = Dirty. Issue bus read. If data is from memory, next state = Valid-Exclusive; otherwise next state = Shared. Issue bus write miss. Write data to cache. Next state = Dirty. Dirty Supply data to processor. Next state = Dirty. Write, no delay. Next state = Dirty. Write old line to memory. Issue bus read. If data is from memory, next state = Valid-Exclusive; otherwise next state = Shared. Write old line back to memory. Issue bus write miss. Write data to cache. Next state = Dirty. Table F.6 Illinois bus actions. State Bus Read Bus Write Miss Bus Invalidation Invalid No Action No Action No Action Valid-Exclusive Supply data. Next state = Shared. Supply data. Next state = Invalid. N/A Shared If highest priority, supply data. Next state = Shared. If highest priority, supply data. Next state = Invalid. Next state = Invalid. Dirty Supply data and update memory. Next state = Shared. Supply data. Next state = Invalid. N/A
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