| Table F.9 Firefly CPU actions. |
|
| State | Read Hit | Write Hit | Read Miss | Write Miss |
| Invalid | N/A | N/A | Issue bus read. If data is from memory, next state = Valid-Exclusive, otherwise next state = Shared. | Issue bus write miss. Write data to cache. If data is from memory, next state = Dirty; otherwise next state = Shared and write data to memory. and other caches sharing it. |
| Valid-Exclusive (or Read Private) | Supply data to processor. Next state = Valid-Exclusive. | Write data, no delay. Next state = Dirty. | Issue bus read. If data is from memory, next state = Valid-Exclusive; otherwise next state = Shared. | Issue bus write miss. Write data to cache. If data is from memory, next state = Dirty; otherwise next state = Shared and write data to memory and other caches sharing it. |
| Shared | Supply data to processor. Next state = Shared. | Write data to mem. and other caches. If no other caches Shared, next state = Valid-Exclusive, otherwise next state = Shared. | Issue bus read. If data is from memory, next state = Valid-Exclusive, otherwise next state = Shared. | Issue bus write miss. Write data to cache. If data is from memory, next state = Dirty, otherwise next state = Shared and write data to memory and other caches sharing it. |
| Dirty | Supply data to processor. Next state = Dirty. | Write data, no delay. Next state = Dirty. | Write old line to memory. Issue bus read. If data is from memory, next state = Valid-Exclusive; otherwise next state = Shared. | Write old line to memory. Issue bus write miss. Write data to cache. If data is from memory, next state = Dirty; otherwise next state = Shared and write data to memory and other caches sharing it. |