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Page 757 Table F.3 Synapse CPU actions. State Read hit Write hit Read miss Write miss Invalid Submit request to read line from main memory. If cache receives a negative acknowledge, resubmit the request. Next state = Valid. Submit bus write miss request. If the cache receives a negative acknowledge, resubmit the request. Next state = Dirty. Valid Supply data to processor. Next state = Valid. Submit bus write miss request. If the cache receives a neg. acknowledge, resubmit the request. Next state = Dirty. Submit request to read line from main memory. If cache receives a negative acknowledge, resubmit the request. Next state = Valid. Submit bus write miss request. If the cache receives a negative acknowledge, resubmit the request. Next state = Dirty. Dirty Supply data to processor. Next state = Dirty. Supply data to processor. Next state = Dirty. Write old line back to memory. Submit request to read line from main memory. If cache receives a negative acknowledge, resubmit the request. Next state = Valid. Write old line back to memory. If cache receives a negative acknowledge, resubmit the request. Next state = Dirty. Table F.4 Synapse bus actions. State Bus Read Bus Write Miss Invalid No action. No action. Valid No action. Next state = Invalid. Dirty Write data back to main memory, send negative acknowledge. Next state = Invalid. Write data back to main memory, send negative acknowledge. Next state = Invalid.
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