| Table F.1 Write-invalidate CPU actions. |
|
| State | Read Hit | Write Hit | Read Miss | Write Miss |
| Invalid | N/A | N/A | Issue bus read. Next state = Valid. | Issue bus write miss. Next state = Dirty. |
| Valid | Supply data to processor. Next state = Valid. | Issue bus invalidation. Write data. Next state = Dirty. | Issue bus read. Next state = Valid. | Issue bus write miss. Next state = Dirty. |
| Dirty | Supply data to processor. Next state = Dirty. | Write data, no delay. Next state = Dirty. | Write old line to memory. Issue bus read. Next state = Valid. | Write old line back to memory. Issue bus write miss. Next state = Dirty. |