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Physically constrained bidirectional bus. |
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Some of the advantages of Rambus DRAMs (RDRAMs) are high bandwidth with small number of chips, large row caches, and good match for frame buffer design. Some of the disadvantages of Rambus DRAMs are its high latency, need to incorporate proprietary macros for bus interface, and the byte serial to word parallel conversion delay. |
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Ramlink is a standard developed by the IEEE Computer Society. The working group applied the techniques adopted in Scalable Coherent Interface (SCI) to develop a ring-topology interconnect memory device. Ramlink also used a high speed byte-wide bus, as in the case of RDRAMs. However, instead of a single short bus, Ramlink uses a ring topology with point-to-point links. As in RDRAMs, Ramlink also has maximum bandwidth of 500MB/s interfaces. The advantage of Ramlink is that it is non-proprietary with a general interconnect. It does not have a physically constrained interconnect bus structure. The disadvantages are longer latency access and lack of availability. |
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TTL voltage levels are logic 0 for 0.8 volt or below, and logic 1 for 2.0 volts or above. Low voltage TTL (LVTTL) changes the maximum input voltage requirement. Rambus Signaling Logic (RSL) specifies a 600mv swing centered at 2.2 volt. Low-voltage differential signalling (LVDS) specifies a 250mv differential swing centered anywhere between 0 and 2v. |
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