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Table 2.1 Pipeline actions and delays.

I fetch includes



		PC ® MAR

4ns



		cache directory access

6ns



		cache data access

10ns



		data transfer to IR

3ns

I decode

12ns

Address Generate

9ns

Address ® MAR

3ns

D fetch includes



		cache directory access

6ns



		cache data access

10ns



		data transfer to ALU

3ns

Execute includes



		R ® ALU ® R

22ns



		Register Put Away

2ns



		We are given:



		k



		=



		clock skew



		=



		0.05



		and



		C



		=



		setup and register delay times (assuming a level-sensitive single-rank register with multiple phase clock)



		=



		4ns



		and



		b



		=



		branch frequency



		=



		.2.



		Then, as a first approximation, the optimum number of pipeline segments (S_opt) is:



		As discussed earlier, S_opt is usually an "upper limit" on a possible number of segments; we initially round down so that



		S_opt = 9.

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