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Figure 2.11
Effect of fraction of pipeline
interruptions (b) on optimum number of
pipeline segments (Sopt). |
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1. Estimate b from instruction set and machine organization characteristics and k from technology considerations, usually k < .1; in the absence of detailed information use k = 0.05. |
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2. Using path delay data, determine T. Find C based on clock design and register delay. |
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3. Compute Sopt. Try various smaller values of S, and hence larger Dt, to find the cycle time that minimizes the quantization effects discussed in the next section. |
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The following study uses what we have learned so far to create an allocation of actions to pipeline segments. |
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Study 2.1 Optimum Pipelining |
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In a certain processor, each instruction requires a number of actions. These actions and their corresponding delays are listed in table 2.1. The delays listed are the nominal values before taking into account any side effects of clock skew and pipeline stage partitioning. |
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Assume that each pipeline segment requires a clock overhead of 4ns and a skew factor k = 0.05; also, the unit delays can be combined into pipeline stages, but can be subdivided into smaller stages only in the case of I-decode (max of 2 6-ns segments) and Execute (into 3 segments, partitioned 7, 7 and 8ns). |
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1. Compute the optimum number of segments (Sopt), assuming a branch frequency b = 0.2. |
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First, we compute T, the sum of all execution phase times. |
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4 + 6 + 10 + 3 + 12 + 9 + 3 + 6 + 10 + 3 + 22 + 2 |
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