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Considering pipeline interruption, the performance of the processor is: |
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The throughput (G) can be defined as: |
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we can find Sopt, the optimum number of pipeline segments [77]: |
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Once an initial S has been determined, the total instruction execution latency Tinstr) is: |
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Finally, we compute the throughput performance G in (million) instructions per second. |
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Suppose T = 120ns and b = 0.2, C = 5ns, k = 0.1. Then Sopt = 10 stages. Figure 2.11 illustrates the effect of pipeline disruptions b on Sopt for these machine parameters. |
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Of course, Sopt as determined is simplisticfunctional units cannot be arbitrarily divided, integer cycle boundaries must be observed, etc. Still, determining Sopt as before can serve as a design starting point or as an important check on an otherwise empirically optimized design. |
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The preceding discussion considers a number of pipeline segments S on the basis of performance. Each time a new pipeline segment is introduced, additional cost is added which is not factored into the analysis. Each new segment requires additional registers and clocking hardware. Because of this, the optimum number of pipeline segments (Sopt) ought to be thought of as a probable upper limit to the number of useful pipeline segments that a particular processor can employ. At the very early stages of any design, when only the estimates for the delay through the various units are known, the initial partitioning of actions into pipeline stages might begin as follows: |
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