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Page 703 Table 10.17 Sample area/cache analysis (fully associative cache). Line Size 4 8 16 32 64 128 Cache size (KB) 64 64 64 64 64 64 Lines 16384 8192 4096 2048 1024 512 Tag bits/line 28 23 22 21 20 19 Tag memory size (KB) 112 46 22 10.5 5 2.375 Total cache size (KB) 176 110 86 74.5 69 66.375 % cache overhead 64% 42% 26% 14% 7% 4% Does it fit? False False False False False True Cache miss rate 0.095 0.052 0.03 0.019 0.011 0.007 Split cache area 184.8 115.5 90.3 78.225 72.45 69.69375 Does split cache fit? False False False False False False sizes. It compares the resulting total area to the available area for cache and narrows down the possible organizations. Given a certain target data cache size, the smaller line size implementations simply do not fit in the given area. Set associativity of 8 gives us the greatest reduction in cache miss ratio, yet provides a relatively low tag memory overhead. Increasing line sizes has the greatest effect in reducing tag memory overhead. Associativity In this study, we assume that the cache implementation is not the critical path of the processor. Increasing the associativity does not penalize cycle time. What we can consider is the area cost due to associativity, along with the cost of comparators. We consider the cases of direct-mapped, 2,4,8 set associative, and fully associative. More associativity reduces the miss rate, but also results in larger tag memory comparator and muxing cost. Memory Design Memory Modeling The memory design has been simplified because of the various assumptions. Since the DRAM chip we are required to use is 4M * 8 with memory size of 64 MB, we can determine the possible interleaving factors: Physical Word Size Interleaving 32b 4 64b 2 The performance increase with wider interface has to be greater than 5% in order to outweigh the 5% cost. Once the interleaving is determined, Tline can be calculated for different line sizes:
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