< previous page page_702 next page >

Page 702
0702-01.gif
Figure 10.10
Percent total cache area used for cache tags.
Set Associative Cache
Tag bits
=
log2 (mem size/cache size) + log2 (degree of assoc.).
Index bits
=
log2 (number of lines/degree of associativity).
Offset bits
=
log2 (number of bytes/line).

Fully Associative Cache
Tag bits
=
log2 (mem size/cache size) + log2 (number of lines).
Index bits
=
0.
Offset bits
=
log2 (number of bytes/line).

For tag memory, four bits are added as control bits. In addition, the direct-mapped cache requires only one comparator, while the set-associative requires as many comparators as its degree of associativity. The fully associative cache requires a content-addressable memory (CAM) as its directory, since every line is a candidate. These memory bits are modeled as 2 rbe each.
Figure 10.10 shows the tag memory area for different configurations and line sizes. The fully associative is prohibitively expensive for small line sizes, so set associativity of eight is chosen.
Table 10.17 shows an example of the analysis carried out across different cache organizations (direct, associative, split versus unified cache) and line

 
< previous page page_702 next page >