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Another decision is whether the addition of a secondary cache boosts performance by more than 20%, to overcome its higher cost of 20%. With the addition of the second-level cache, CPI computation is as follows: |
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CPI.2nd cache = |
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CPI.Base + TLB.penalty |
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+ DR/cycle * D - cache.MR * (Taccess.L2 + (L/W - 1) Tcycle.L2) |
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+ Cache.L2.MR/D - cache.MR * Tline/cycle time |
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+ I - cache.MR * IR/cycle * (Taccess.L2 + (L/W - 1)Tcycle.L2) |
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+ Cache.L2.MR/I - cache.MR * Tline/cycle time. |
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The following assumptions were made in generating the preceding model: |
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The secondary cache is CBWA. |
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The secondary line size is 128 bytes. |
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Of course, there may be cases of contention in the second-level cache, as in a unified cache, but since the on-chip cache and write assembly cache are able to filter out most of the requests, we assume that instruction references do not collide with data references in the analysis. |
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A secondary cache serves as intermediate storage between the processor and main memory. It buffers the processor from traffic on the memory bus and can reduce the amount of traffic on the bus. This is especially critical in a multiprocessor system where we want to avoid bus saturation and isolate coherent traffic from the processor. Most secondary caches are managed using CBWA to reduce write traffic on the shared bus. To reduce coherent traffic interference, the first-level cache is WTNWA to keep the secondary cache consistent with the first-level cache. |
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When a bus is accessed by multiple users, one can have contention among the users. A simple model is one that takes into account the occupancy of the bus by users. We follow the model presented in chapter 6. |
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The previous section detailed the models and qualitative discussion of various implementation options. In this section, we present results of the analysis. Of course, only a small part of the data can be presented because of space limitations. Most of the data shown is for the 0.75m case, and we discuss results from the other feature sizes. |
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