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Page 701 Table 10.16 Cache/memory interface options. Option 1 Option 2 Option 3 Write dirty line to memory Fetch new line Fetch missing word first Fetch new line Start processor Start processor Start processor Write dirty line to buffer Finish line fetch and write dirty line to buffer Tm.miss = (1 + w)Tline Tm.miss = (1 + w)Tline Tm.miss = (1 + w)Tline Tc.miss = (1 + w)Tline Tc.miss = Tline Tc.miss = Taccess Tbusy = 0 Tbusy = wTline Tbusy = (1 + w)Tline - Taccess For CBWA, there are three combinations shown in Table 10.16. Line Size Line size is the unit of transfer between cache and memory. The selection of line size is critical for processor performance. Altering the line size affects the following: Cache miss rate. Memory traffic. Tag memory size for cache directory. Increasing or decreasing the line size is a decision based on balancing cache miss rate, memory traffic, and tag memory size. Increasing the line size decreases the miss rate due to the enhanced spatial locality of the cache (sequential address request). However, the decreases in miss ratio become smaller as we increase the line size further, since the cache is losing its temporal locality (fewer lines). The optimum point is reached when the effect of decreasing the miss ratio no longer compensates for the increase in Tline. Increasing the line size decreases the number of lines in the cache, thus decreasing the overhead of tag memory associated with each line. With small caches, if we increase the line size too much, we hurt the temporal locality of the cache, since we tend to replace lines too often due to the low number of lines available. Tag Memory Modeling A physical address is broken into the following: Direct Map Cache Tag bits = log2 (mem size/cache size). Index bits log2 (number of lines). Offset bits = log2 (number of bytes/line).
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