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Page 700 (table continued from previous page) Tc.miss = Time processor is stalled due to a read miss Twrite.mem = Time memory is busy due to a write miss Twrite.c = Time processor is stalled due to a write miss Tbusy (Read) = Tm.miss - Tc.miss. This is the time period where CPU is free to make further requests while the memory is still busy. For write buffer number 1: Tm.miss = Tline Tc.miss = Tline Twrite.mem = max(Taccess, Tcycle) Twrite.c = 0 Tbusy (Read) = 0. Since Tbusy(Read) = 0, no memory contention can occur due to a read blocking another read. However, a write that is being serviced can block a read request, and is accounted for in Tw.interference. The first term, 1 - (1 - Reads/cycle)Twrite.mem/cycletime, is the probability of a read request during the number of cycles it takes to process the write request. The second term, Writes/cycle, is the probability of a write request during any cycle. The third term, Twrite.mem/2, is the average waiting time of a read request. After including the write interference time, the time to process a read is: Tc.miss = Tline + Tw.interference. For write-through cache with buffer 2, we have the following: Tm.miss = Tline Tc.miss = Taccess Twrite.mem = max(Taccess, Tcycle) Twrite.c = 0 For this case, a read in progress can block an upcoming read, since Tbusy = Tline - Taccess. As a result, we must also include Tr.interference in the final read processing time of memory. For CBWA, there are three combinations shown in Table 10.16.
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