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Page 693 Table 10.14 Multiprocessor area. Integer ALU 1.00 FP multiplier 20.3 Integer register 1.00 Divide supprot 3 Shifter 0.50 FP unit 37.8 Incrementor 0.40 2x FP unit 75.6 PC unit 1.00 2 TLBs 6.00 Latches 10.68 Decode + control 1.00 Bus 42.72 Cache controller 1.00 Bus logic 2.00 Total multiprocessors 160.20 Stored buffer + bypass 1.00 Load/store 0.20 Die area 230 Clock generator 1.00 Area available 184 Integer unit 16.10 Area in ''A" 335.11 Added branch adder 1.00 Remaining area 174.91 2x integer unit 34.20 10% aspect ratio 17.49 Remove one TLB 3.00 Cache area 157.41 Total integer 31.20 FP RegFile 1 Cache bits 388,289.96 FP adder 13.5 Cache KB 47.40 In-Line Traffic The in-line reference traffic is calculated as follows: Iin-line = (1/m) * IF access time * instr/IF, wherem is the number of cycles between instruction issues, IF access time is the number of cycles required per access, and instructions per IF is the width of the interface between the I-cache and the I-buffer. For the baseline case: m = 1 (maximum of 1 instruction decoded per cycle). IF access time = 1 cycle. Instructions per IF = 1 or 2 (interface width of 4 or 8 bytes). Instr/IF I (in-line) 1 1 2 0.5
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