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Page 692 Table 10.13 Superscalar processor area. Integer ALU 1.00 FP RegFile 1 Integer register 1.00 FP adder 13.5 Shifter 0.50 FP multiplier 20.3 Incrementor 0.40 Divide support 3 PC unit 1.00 FP unit 37.8 2 TLBs 6.00 Added pipeline 12 Decode + control 1.00 Total FP 49.8 Cache controller 1.00 Bus logic 2.00 Stored buffer + bypass 1.00 Load/store 0.20 Clock generator 1.00 Integer unit 16.10 Added branch adder 1.00 Latches 7.062 Additional integer unit 1.00 Bus 28.248 Additional buffer 1.00 Additional decoder 1.00 Added port/RegFile 0.32 Added bypass network 0.40 Total integer 20.82 Total superscalar 105.93 Remaining area 229.18 10% aspect ratio 22.92 Die area 230 Cache area 206.26 Area available 184 Cache bits 508,769.36 Area in "A" 335.11 Cache KB 62.11 1. The bandwidth from the primary cache to the I-buffer meets or exceeds the maximum request rate of the processor. 2. There are enough entries in the I-buffer to avoid buffer runout. 3. The I-buffer consists of one or several instruction registers that hold the current instruction being decoded, an alternate path buffer, and a primary path buffer. From the preceding requirements, the important design parameters of the I-buffer are: The width of the memory interface and the access time per I-fetch. The number of in-line and alternate path buffers. Branch instruction frequency, behavior, and branch management scheme.
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