| Table 10.9 Given conditions. |
|
| Area (from Study 2.3) |
| Total chip area | 230 mm2 |
| I/O pad overhead | 20% |
| Latch overhead | 10% of Integer and FP units |
| Bus overhead | 40% of Integer and FP units |
| Aspect ratio mismatch overhead | 10% of cache area |
| Base CPI (given) | |
| Implementation type | Base CPI |
| Baseline processor | 1.47 |
| Superscalar processor | 0.833 |
| Multiprocessor processor | 0.795 |
| References per instruction (given) | |
| Instruction references | 1 (approximation) |
| Data Read references | 0.31 |
| Data Write references | 0.20 |
| Timing specifications (given) | |
| Cycle time | 8 ns |
| Memory Taccess | 96 ns |
| Memory Tcycle | 60 ns |
| Memory Tc | 16 ns |
| Memory Tbus | 8 ns |
| On-chip cache access | 8 ns |
| L2 cache Taccess | 24 ns |
| Memory specifications (given) | |
| Memory size | 64MB |
| Types | 4M ´ 8b |
| Fast sequential page mode | Available |
| Interleaving | To be determined |
| TLB specifications (given) | |
| Number of entries | 128 |
| Associativity | 2 way |
| Page size | 4KB |
| TLB miss rate | 0.0065 (Table 5.48) |
| TLB miss penalty | 20 cycles |
| Secondary cache specifications (given) | |
| Size | 256KB |
| Organization | Direct-mapped |