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10.2 Area Performance Analysis of Processors |
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As integrated circuit density increases, computer architects face the interesting problem of how best to utilize the available die size given cost and performance constraints. It is now commonplace to have more than 3 million transistors on a single chip with over 500 pins. Table 2.3 details some of the state-of-the-art implementations currently available. |
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The architect faces the complex problem of how to balance performance against complexity and design time. Since the lifetime of a microprocessor is about two years, the architect must examine ways to use the advances in IC technology and design a microprocessor that fits the needs of the target market in terms of performance, power consumption, and cost. It is an exciting challenge to define a new architecture or to extend an older architecture at the instruction level. |
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Are the added capabilities adequately utilized by the workload? Instruction sets change in response to technology and anticipated application needs. Some recent examples of this evolution are the shift to 64-bit architectures and the inclusion of instructions to enhance graphics operations. The software effort of revamping the architecture requires redevelopment of the operating system and compiler, and can be a lengthy effort. To accommodate backward compatibility, hardware and software emulations are frequently run. This comes at a cost: an example is the Intel Pentium, where reportedly more than 15% of the area is used to support emulation. |
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With added performance and complexity comes higher cost for the processor chip. Is the customer willing to pay for the increased performance? |
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The previous study evaluated and compared two possible incremental changes: |
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This study looks at different implementations, as it is possible to mix and match different configurations of the core processor, floating point unit, memory hierarchy, and external bus interfaces using predefined modules. Using such a modular design style has many advantages. A company can create a family of processors with different cost, performance, and power utilization at the ''press of a button." "Press of a button" is definitely an oversimplification, since there are specific techniques that must be used to reduce cost and power. Having a family of processors based on different configurations of modules offers the company the luxury of attacking different market segments: scientific servers, workstations, PCs, laptops, and the embedded processing market. |
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This study details the design of a load/store processor to be used as the core of a high-performance system. It could be the processing engine of a scalable multiprocessor system. A specific goal of this study is to investigate how varying the feature size, thus increasing or decreasing the transistor count, affects the CPI of the different implementations. This also gives the designer a sense of the future direction of microprocessors. |
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