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Figure 10.6
Performance with 7.5-cycle cache miss penalty. |
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more so, the faster the memory system appears to the processor. However, when reducing the performance of the memory system, it is clear that the memory system becomes the determining factor for performanceif the memory system appears "slow" to the processor, then the super-pipelined processor is a slight loser. In fact, for page fault penalties greater than 30 cycles, the super-pipelined processor is never better than the reduced-scale processor. Whether or not this poses a problem is determined by marketing's goals and engineering's ability to scale up memory system performance with processor performanceif marketing has plans for offering systems with lower performance than the current 5-cycles memory system penalty, there may be justification for developing both processors; if marketing plans to offer only systems with increased memory system performance, there is little question that the super-pipelined processor is the better choice to pursue, provided that the designers account for a learning curve that reduces the defect density in a reasonable amount of time. |
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It is clear that a myriad of design choices is available and that these choices are not based purely on engineering and performance considerations. However, given a set of constraints that must be met, an estimation of the expected performance is fairly easy to work through using data of the sort provided here. The data may be acquired from a number of different sources (as is the data in this book) or may be specifically measured for the application at hand;it makes no difference to the application of the data. Calculations as performed in this study, however, should be used as coarse predictions of performance. More accurate results may be needed to base final design decisions on, and will require much more detailed and careful calculations and measurements, possibly including a full processor and system simulation to adequately gauge the tradeoffs. |
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