< previous page	page_678	next page >
Page 678 Table 10.7 Memory system delays. Miss Penalty Reduced-Scale Super-Pipelined Cache 0.670 cycles 0.895 cycles TLB 0.080 cycles 0.130 cycles Total Memory 0.750 cycles 1.025 cycles Table 10.8 Processor system instruction cycle summary. Delay Source Reduced-scale Super-pipelined Instruction 1.000 cycles 0.500 cycles Pipeline 0.795 cycles 0.928 cycles Memory 0.750 cycles 1.025 cycles Total 2.545 cycles 2.453 cycles the reduced-scale and super-pipelined processorsis now easy to determine. First, using the Poisson model, we get a yield of: The 8-inch wafer gives a total die count of: Since there is an 11.3% yield, we get a total of 127 ´ 0.113 = 14.4 average good dies per wafer. The cost per chip is thus the packaging cost for a chip plus the net cost per die, or for the Baseline Mark I processor. Similarly, for the reduced-scale and super-pipelined processers, respectively, we get yields of 10.3% and 9.5%, areas of 2.269 cm and 2.359 cm, wafer counts of 122 and 117, average good dies per wafer of 12.6 and 11.1, and costs per chip of $496.8 and $550.5. Thus, the reduced-scale processor costs $49.6 (11.1%) more, and the superpipelined processor $103.3 (23.1%) more, than the original processor.
< previous page	page_678	next page >