The reduced-scale version of this processor has a 0-cycle delay for this sequence of instructions.
The super-pipelined version of this processor has a half-cycle delay, since the write phase is slipped back a half-cycle, causing a stall to be needed.
BRANCH (assume in-line)
This examines the pipelines for both unconditional branch (jump) and conditional branch instructions.
For the reduced-scale version of the processor:
- Unconditional case
There is no unconditional branch assumed to go in-line!
- Conditional case
There is a 0-cycle delay for in-line, a 2-cycle delay for target, one unused in-line instruction fetched on branch to target, and no unused target instructions fetched on continue in-line.
For the super-pipelined version of the processor:
- Unconditional case
There is no unconditional branch assumed to go in-line!
