For the reduced-scale version of the processor, this sequence of instructions results in a 0-cycle delay.
However, since the AG and EX phases of the instruction are overlaid in the pipeline, this sequence of instructions results in a half-cycle delay.
LD/EX
This sequence of instructions consists of a load instruction followed by an ALU operation instruction, using data from the load.
The reduced-scale version of this processor has a one-cycle delay due to the additional cycle required to access the memory system (first-level cache).
The super-pipelined version of this processor saves a half-cycle here for a half-cycle delay.
EX/ST
This sequence of instructions consists of an ALU operation instruction followed by a store instruction using data from the ALU operation.
There is a 0-cycle delay for this sequence on the reduced-scale version of this processor.
Since the result of the ALU operation is not needed for the AG phase, there is a 0-cycle delay in the super-pipelined version of this processor.
LD/ST
This sequence of instructions implements a memory-memory move using a load instruction followed by a store instruction.
