Figure 10.1
Baseline Mark I pipeline timing template.
Figure 10.2
Baseline Mark II pipeline timing templates. (a)
Reduced-scale processor. (b) Super-pipelined
processor.
For each type of instruction pairing where there is a dependency (such as EX/EX) between the two instructions, we examine in detail the pipeline operation for each machine. The results are then tabulated and a pipeline penalty computed based on the data in Chapters 3 and 4. For each pair, the reduced-scale processor is considered first and the super-pipelined processor is considered next.
EX/EX
This is a sequence of any two ALU operation instructions.
For the reduced-scale version of the processor, this sequence of instructions results in a 0-cycle delay.
However, for the super-pipelined version of this processor there is a half-cycle delay from this sequence of instructions. This is because the execution phase of this machine occupies two cycles, and the second instruction requires the data from the first instruction and so must stall for one cycle.
EX/AG
This is a sequence of instructions with an ALU operation first and a load, store, or branch operation second.
