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Page 666 Table 10.1 Baseline Mark I area model. Integer Unit Area Components Integer ALU 1.0A Integer register file with bypassa 1.15A Shifter 0.5A Incrementer 0.4A Program counter unit 0.85A TLBb 6.0A Decoder hardware 1.0A Cache controller 1.0A Bus logic 2.0A Store buffer 1.0A Load/Store byte support 0.2A Clock generation 1.0A Total integer unit area 16.1A Floating Point Unit Area Components Register filec 1.0A Adder 13.5A Multiplier 20.3A Division supportd 3.0A Total floating-point unit area 37.8A Memory Subsystem Area Components 16 KBI-cachee 53.1A 8 KBD-cachef 26.6A Total memory subsystem area 79.7A Processor Overhead Area Components Integer unit (50%) 8.05A Floating-point unit (50%) 18.9A Memory subsystem (15%) 14.05A Total processor overhead area 41A Die Area Components Total processor area 174.6A Die overhead area (20% total processor area) 43.7A Total die area 218.3A aThe integer register file consists of 32 single-word integer registers that are paired to support double word values. bThere are two TLB's, each of which is 2-way set-associative with LRU replacement and each has 128 entries (64 ´ 2). cThe floating point register file consists of 32 IEEE Single Precision registers that are paired to support Double Precision values. dAdditional area allows multiplier to perform divisiona separate divider element would require 23.3A, which includes both a multiplier and division support. eThe cache is 8kB direct mapped, 4 word per line (16 byte per line), write-through no write-allocate. fThe D-cache is a copyback cache. Both caches have 16 bytes per line and are 4-way set-associative.
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