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The fabrication line for this processor uses 8-inch (20.32 cm) wafers and has a cost per wafer of $5,000, including wafer-level testing and sorting. Packaging cost for this chip is $100 per package and includes final chip-level testing. |
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When necessary, further assumptions will be made in order to make design decisionsan occurrence that is not infrequent in real design processes. However, these are most of the basic bookkeeping assumptions that will be required during the course of the study. |
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10.1.2 Design Alternatives |
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We use the standard area model to determine the size of the die. Table 10.1 shows the Baseline Mark I processor area breakdown, using the standard area model. |
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Beginning with this breakdown, we extend the processor to improve the performance of the machine. In order to understand the different tradeoffs involved, two different designs are evaluated. |
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A three-quarter-scale reduction of the original baseline unit, in order to expand the cache and TLB available on-chip in the hope of increasing performance due to the reduced miss penalty. This uses the same area as the original processor. |
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A super-pipelined version of the original design, which (due to conservative design practices) will be designed at full scale. |
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We assume no cycle time reduction for the reduced-scale processor, nor do we assume any cycle time penalty for the super-pipelined processor for simplicity. However, we will add a 10% penalty to the pipeline, cache, and TLB for the super-pipelined processor to account for the additional latch and control logic that the super-pipelined processor requires. The die overhead remains constant at the original Baseline Mark I value. |
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The pipeline for the original processor is shown in Figure 10.1. The pipeline for the first new design is the same as the original processor, and is shown in Figure 10.2(a). The pipeline for the second design is the half-cycle version of the original processor pipeline, and is shown in Figure 10.2(b). Since the goal of these processors is to fit into the same framework as the original processor, the times are all normalized to the original processorthus, the reduced-scale version has a cycle time of "one cycle" and the super-pipelined version has a cycle time of "one half-cycle" for all calculations performed in the study. |
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10.1.3 Pipeline Timing Analysis |
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In order to determine what the tradeoffs are for the two design choices described in section 10.1.1, we must consider both performance and cost. This section evaluates the two pipelines for performance. We consider cost effects in the next section, using different system configurations for these two designs. |
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