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Figure 2.1
Possible sequence of actions within a cycle. |
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time, all registers may be sampled by an edge or pulse produced by the clocking system. |
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Frequently, the control decoding and accessing of control point values for the next cycle are overlapped with the application of control signals for the current cycle. See also problem 2 in Chapter 1. |
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In a synchronous system, the cycle time is usually determined by assuming the worst-case times for each step or action within the cycle. Finally, the clock itself may not arrive at the anticipated time (due to propagation or loading effects). We call the maximum deviation from the expected time of clock arrival the (uncontrolled) clock skew. In the alternative asynchronous system, the cycle time is determined by the completion of the event of interest. A completion signal must be generated, which then allows the next operation to commence activity. Asynchronous clocking is not generally used within pipelined processors because of the completion signal overhead and pipeline timing constraints. |
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2.2.2 Partitioning Instruction Execution into Cycles |
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The execution of an instruction consists of a sequence of events or actions specified by the instruction semantics. In Chapter 1, we assumed that the time required for each event had been nicely packaged into one or more cycles. In this section, we look at this partitioning problem. |
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Instruction execution has at least the following actions, which are usually executed in sequential order: |
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1. Instruction Fetch (IF): the cycles required to fetch the contents of the address in the instruction counter into the instruction register (IR). |
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2. Decode (D): the cycles required to initialize the interpretation (execution) process. |
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3. Register Fetch (RF): the cycle to fetch register operands. |
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4. Address Generate (AG): the cycles required to generate the effective memory address of the data operand or the target instruction (in the case of branch). |
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