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The notion of time receives considerable attention from processor designers. It is the basic measure of performance; but breaking actions into cycles and reducing both cycle count and cycle times are important but inexact sciences. The partitioning of actions into cycles can "make or break" a design. Many a design was crippled by an unanticipated "extra" cycle required by a basic action such as cache access. |
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Overall, there is only a limited theoretical basis for cycle selection and the resultant partitioning of instruction execution into cycles. Much design is done on a pragmatic basis. This section covers some more commonly used models of cycle time determination and instruction execution time partitioning. |
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In this section, we look at some techniques for instruction partitioning, that is, techniques for breaking up the instruction execution time into manageable and fixed time cycles, In a pipelined processor, data flows through stages much as items flow on an assembly line. At the end of each stage, a result is passed on to a subsequent stage and new data enter. Within limits, the shorter the cycle time, the more productive the pipeline. The partitioning process has its own overhead, however, and very short cycle times become dominated by this overhead. Simple cycle time models can optimize the number of pipeline stages. Reliable operation is another issue that the designer must keep in mind. This includes the clocking approach itself, the relationship between the clock pulses that sample data into registers, and the determination of whether or not there are hazards for data entering registers. Finally, we look at the concept of a minimum achievable cycle time and what it takes to realize such a cycle. |
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Cycle time is the essential quantumthe building blockof pipeline processor design. |
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2.2.1 The Nature of a Cycle |
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A cycleis the basic time quantum for processing or communicating information within a machine. A cycle is defined as the time between state transitions. The designer determines the cycle time by finding the worst-case (maximum) time to accomplish a meaningful event (or operation) across the most frequently used data paths. This time must be sufficient for data to be safely sampled into designated destination registers (Figure 2.1). Less frequently used paths that require more time to complete than this require multiple cycles. |
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A cycle may begin with the new value of the sequence counter or microinstruction address being entered into the decoder. The decoder then provides a control vector (set of control point values) to its output register (or the microinstruction register, for microprogrammed machines). This control vector (or microinstruction) defines a control value that may be further decoded so that each control point has a distinct value. These control points are then applied to the various data path output register gates and combinatorial logic throughout the system (Figure 2.1). This allows data from source registers to propagate through designated combinatorial logic into the in-gating of the destination register. Finally, after a suitable setup |
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