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Chapter 2
The Basics: Time, Area, and Instruction Sets |
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The tradeoff of cost and performance is fundamental to any system design. Different designs result either from the selection of different points on the cost-performance continuum, or from differing assumptions about the nature of cost or performance. |
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In this chapter, we deal with three conceptual areas. The first area is time, which includes partitioning instructions into events or cycles, basic pipelining mechanisms used in speeding up instruction execution, and cycle time as a parameter for optimizing program execution. Second, we discuss area. The cost or area occupied by a particular feature is another important aspect of the architectural tradeoff. Third, instruction sets affect both performance and implementation. Instruction sets that require more implementation area are less valuable than instruction sets that use lessunless, of course, they can provide commensurately better performance. Long-term cost-performance ratio is the basis for most design decisions. By looking at instruction sets and their implementation requirements, we can draw some conclusions about the cost effectiveness of some architectural choices. The goal of this chapter is to provide a basis for cost-performance evaluation as it affects instruction set decisions. |
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The chapter begins with the machine cyclespecifically, how much delay is incurred in a cycle, how instruction execution is partitioned into cycles, and how clocking can be made reliable. We next look at pipelined machines: machines that overlap the execution of multiple instructions in order to speed up program execution. For such processors, we can approximately determine the optimum cycle time. Nothing in machine design is "free,"so a cost (area) model is introduced to assist in making instruction set tradeoffs. This model is restricted to on-chip or microprocessor-type tradeoffs, but it illustrates a type of model that the designer must use in all machine designs. Finally, we look at the instruction set data relative to high-level language program actions, and then at tradeoffs between instruction code density and register size. |
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