If the leading microinstruction bits are "01," then the opcode bits of the IR are loaded into the lowest eight bits of the ¨MAR and the upper bits are cleared and the indicated address is fetched into the ÏR (microinstruction register). The opcode bits in the IR thus form a pointer to a table (the first 256 entries in microprogram storage). Each entry specifies the address of the microprogram routine executing the designated op.
If the leading microinstruction bits are "10," then an unconditional branch occurs in the microcode. The lowest 12 bits of the microinstruction are gated to the micromemory address register (¨MAR).
If the leading microinstruction bits are "11," then a conditional branch occurs. The microinstruction contains an address test vector. If any of the specified tests are satisfied, the branch is taken and the address is placed in the microinstruction address register; otherwise, sequencing continues in line.
The test vector tests:
1. TEMP overflow (carryout).
2. TEMP negative.
3. TEMP zero.
4. Value in R2 is NEG.
5. Value in R3 is NEG.
6. CC bits in IR "AND"ed with the CC bits in PSW and then "OR"ed. Result is a ''1."
Write the microcode and show instruction timing (through the fetch of the next instruction) for the following instructions, assuming that the instruction is already in the IR:
