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(a) ADD R1, R2, R3 (absolutei.e., unsignednumbers) |
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(b) LD R2, #A (the immediate value, A, is stored in the address portion of the IR) |
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(c) LD R2, Addr[R3] |
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Assume memory access = memory write time = 3 cycles. |
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BC.NE Target [R3]
ST Addr [R3, R1]
SUB R1, R2, R3 |
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4. Extend the processor (data paths and ICPs) described in problem 2 to execute |
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MPY R1, R2, R3 |
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Then show the microcode and timing. |
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5. Suppose the microcode access time is overlapped with the c.p. control of the data path. Microinstructions must now be fetched one cycle early. What will be the effect on the following image instructions? |
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(a) BC.NE Target [R2] |
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(b) LD R2, Addr [R1] |
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Assume the overlap facility allows cycles to execute at 1/2 the time indicated in problems 24. Do either of these instructions require extra cycles (more than the unoverlapped host machine)? |
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6. Evaluate the effects of the following proposed host improvements on cycle count on various instructions considered in problems 2 and 3. |
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(a) Reduce memory access/store time to two cycles. |
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(b) Use a three-ported register set (i.e., eliminate TEMP and allow R1 op R2 ® R3 in one cycle). |
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7. Suppose an interrupt occurs in problem 2 after an I-fetch but before instruction execution has occurred. |
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A special interrupt bit is set. Extend the host machine (microinstruction, etc.) to handle this and describe the resulting action. |
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8. A certain computation results in the following (hexadecimal) representation: |
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Show the floating-point representation for the preceding in: |
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(a) IBM long format. |
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(b) IEEE short format. |
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(c) IEEE long format. |
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