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5 ´ 1.3 ´ 1.5 = 9.75 transactions per 100 instructions |
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10.26 instructions per transaction. |
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This slows down the processor from operating at 7.73 MIPS (no contention) to 7.27 MIPS. |
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(b) Shared-bus multiprocessors without bus contention and with memory contention |
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Now suppose each processor has its own bus (ideal bus), and the memory system has two independent modules each capable of a line access. They are interleaved on low-order line address, and any single module is busy for Tline access for each line access (i.e., page mode). |
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We now use the d-binomial model from chapter 6 to compute the memory performance: |
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Now m = 2 and we must find n and d. |
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We compute n as the expected number of requests during Tline access. Each processor makes: |
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5.85 references ´ 0.05 misses/reference |
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= 0.29 miss requests/line access. |
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Therefore, for four processors: |
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Since we have three request sources each cycle (IF, DF, DS) and three cycles per memory busy time (line access, in this case), we have z = 3 ´ 3 ´ 4 (processors) = 36. So |
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Now, using the d-binomial equation, we compute: |
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B(m = 2, n = 1.16, d = 0.03) = 0.85 |
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