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Page 553 Study 8.2 Shared-Bus Multiprocessors (a) Shared-bus multiprocessors with bus contention Suppose four processors with CBWA caches share a common bus and memory system. Initially, we assume that there is no contention at the memoryonly at the bus. Suppose we are given the following processor parameters: Processor performance: 10 MIPS (all in cache). References per instr: 1.3 (total from IF, DF and DS). Cache miss rate: 0.05. w, dirty line ratio: 0.5. Bus transaction = Tline access = 300 nsec. We now look at the effects of bus contention on overall performance. First we compute: Total processor execution time including bus transactions = 12.93. or, with resubmissions (after several iterations): a = .273 ra = .18 B (n = 4) = 0.72 We offered 0.92 of the total bus capacity, and achieved 0.72. The effect of this was to slow down each bus transaction by: The effect of this delay on processor performance is to wait for 83.3ns. Thus, there are:
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