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As mentioned in chapter 6, this ignores the obvious fact that a request to the bus that has been denied will be immediately resubmitted and wait until the bus is available. The net effect of this is to increase the actual realized bus bandwidth over that expected by the above analysis. As developed in chapter 6, we estimate the actual bus requests (a) per source [307] as: |
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Initially estimate a = r, and then we can iteratively solve for a and ra. |
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Processors slow down due to bus contention. They achieve only bus transaction rates (and hence performance) of la when offered rates of l. The expected delay due to bus contention for each transaction is: |
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so that the offered rate, l, is: |
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l = 1/processor execution time + bus time, |
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This is the effective ''slowdown" factor due to bus contention. Since we are primarily interested in the la/l ratio, we can compute the rates in terms of processor execution (MIPS) or bus transactions. |
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If a 10-MIPS processor has 9.75 misses per 100 instructions and each miss creates a 300-nsec bus transaction delay, then the offered rate is: |
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The processor execution time between bus transactions is 100/9.75 instructions: |
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In terms of processor performance, the bus adds 300ns/10.26 instr = 29.2 ns to each instruction, or: |
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