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Page 551 8.9.2 Bus-Based Models These are the simplest analytic models. While useful across a variety of applications (including memory), they are probably most appropriate for the analysis of bus contention when a bus is being accessed by multiple users (processors, etc.). We refer to a similar model of memory contention in chapter 6Strecker's model [273]. For bus contention, assume there are n requestors each of which would occupy the bus for a fraction of time r. This factor r is akin to the queueing utilization factor r. It represents the offered amount of occupancy by a single source without contention. The model assumes that the bus has no memory. Its state at any time does not depend on previous history (number of requests denied, etc.), or on its immediate history in the case of resubmitted requests. The bus utilization generally is: where (in terms of 100 instructions): Bus transaction time is the time spent on the bus (excluding waiting time) per 100 instructions executed, and Processor time is the execution time per 100 instructions, excluding bus transactions. If processor execution and bus transaction time are overlapped, the processor time is the unoverlapped processor execution. A simple CBWA cache-based processor might have: Bus transaction time = 100f(1 + w)Tline access, where f is the miss rate per reference. Once r has been determined, we have for n processors sharing the bus: Prob [a given processor does not reference but] = (1 - r) Prob [no processor references but] = (1 - r)n Prob [bus is busy] = 1 - (1 - r)n =B(n) where B(n) is the achieved bandwidth as a fraction of the total available bus bandwidth. Note that: 1. Offered bandwidth = nr. 2. Total available bus bandwidth = 1.0. 3. Achieved bus bandwidth = B(n).
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