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Figure 1.25
Data paths for a nonpipelined R/M processor. |
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Note 1 This instruction could be eliminated by using R0 as the index register in instruction sets where R0 always contains zero. We have assumed that a cache miss occurred during instruction fetch. The miss is assumed to bring a line of instructions into the cache, including the subsequent instructions. |
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We assume that the cache line is sufficiently large to contain the remainder of the instructions. Also note that since this instruction occupies two bytes, we increment |
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