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Figure 7.40
Multiple issuing schemes. |
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Instruction 4 depends upon instruction 3 only insofar as it uses R1. By assigning R1 in I3 to a shadow register (or a second register set), we avoid the dependency. If there are sufficiently large register sets, there is little need for shadow registers, since the compiler can reduce the conflicting use of registers as shown in the preceding example. Similarly, the hardware can accomplish the same thing by using registers that are not visible to the instruction set; for example, if the instruction set had eight registers specified in the preceding example, the decoder could simply relabel the second use of register 1 as register 9. |
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Thus, shadow registers, extended register sets as used by the compiler, and reservation stations are alternate approaches for achieving a generally equivalent effecteliminating ordering and output dependencies. |
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The Cost of Simultaneously Issuing Multiple InstructionsSimple Approaches |
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The simplest type of multiple-issuing scheme is a partitioned or fragmentary occurrence (Figure 7.40). In this type of scheme, concurrent execution occurs only if certain types of pairs or triples of instructions occur in a sequence: |
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1. Fixed-Point/Floating-Point Here, any fixed-point instruction (i.e., one based upon the general-purpose registers) may be simultaneously executed with any instruction that is based only on the floating-point |
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