|
|
|
|
|
|
|
registers. Clearly, there is no dependency between the two instructions, and therefore dependency analysis is avoided. Sequences such as: |
|
|
|
 |
|
|
|
|
ADD R1, R2, R3
ADD.F R1, R3, R4 |
|
|
|
|
|
|
|
|
can be handled easily, since the register sets and functional units involved are different. Of course, convert instruction (e.g., convert to floating-point), which uses both register sets, must be recognized as exceptional. |
|
|
|
|
|
|
|
|
2. Load/ALU/Branch Another type of concurrency can be achieved by allowing the issuance of a load or a store instruction simultaneously with a functional instruction, and/or perhaps even a branch instruction. A branch tests the results of a previous instruction, the ALU instruction (register-based) modifies the current register set state, and the load instruction prepares the register set for the next instruction. This type of concurrency is more common in highly microprogrammed machines, but has been useful in modern machine design [57]. It ensures the more regular use of resources. Note that with the floating/fixed-point operation, the two instructions may contend for memory resources, which is less likely to happen with the second type of partition concurrency. |
|
|
|
|
|
|
|
|
3. Composite Instructions Special instructions can be added to a processor repertoire to increase performance. A classic example is the combined floating multiply instruction, whose product is accumulated (added to) the content of a designated register. The accumulator add can be performed while the final product is being computed, reducing the add time. The occurrence of MAD.F opportunities seems high enough in certain benchmarks to consider its adoption for marketing purposes, if no other. |
|
|
|
|
|
|
|
|
The Cost of Simultaneously Issuing Multiple InstructionsGeneral Approaches |
|
|
|
|
|
|
|
|
For more robust and generalized issue of multiple instructions, the equivalent of a dependency matrix is required. For control flow, this is accomplished by extending the interlock logic of study 4.9. Now each instruction in the issue window must compare its sources to the destinations of instructions that occur earlier in instruction sequence in the window and to the destinations of previously issued but uncompleted instructions. |
|
|
|
|
|
|
|
|
Assume that we compare N instructions each cycle. In order to check for essential dependencies, each source operand specifier has to be compared with the destination of all instructions that occur earlier in the sequence in |
|
|
|
|
|