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For a control flow machine (improved scoreboard), the situation is somewhat different. Now *[MPY R1,R6,R7] cannot be issued, as the R1 tag cannot be overwritten. Only after the result of the multiply [MPY-0] is placed in R1 will the R1 tag be reset, enabling * to be issued. For instruction * + 1 [ADD] and * + 2 [DIV], the situation is exactly the same as with dataflow. Both instructions are held at the issue stage, but now * + 3 [MPY] can be issued (unlike dataflow), since the multiplier reservation station is available. |
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In summary, |
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Only * + 3 MPY R2,R11,R12 is issued. |
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It causes the R2 tag to be [MPY-1]; the other tags are unchanged. |
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The first three (*, * + 1, * + 2) instructions are held in the issue stage. |
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Renaming and Shadow Effects |
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Using multiple value-holding reservation stations and labeling them separately allows the decoder to distinguish among the users of a resource. Consider the following example: |
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I1 ADD R1, R7, R8
I2 MPY R3, R1, R2
I3 MPY R6, R4, R5
I4 ST ALPHA, R6. |
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Assume a multiplier with two (sets of) value-holding reservation stations, MPY1 and MPY2. The decoder issues I2 and I3 on successive cycles to reservation stations MPY1 and MPY2, respectively. Since MPY1 has a tag for a value from the ADD (the R1 value), it cannot proceed, but MPY2 begins execution when I3 is issued, because the multiplier and the operands are available. When I4 is issued, R6 gets the TAG_MPY2, which is forwarded to the store buffer. |
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In the preceding example, the results of the two multiplies are distinguished by their unique tags; thus, the functional units that use the result of multiply 2 are distinguished from those using multiply 1, regardless of the order in which these multiplies are actually executed. |
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An analogous arrangement can be achieved by using shadow registers. Shadow registers are duplicate registers or sets of registers that allow the decoder to ''rename" a sequence of code with new register values. Thus, suppose we have code in this sequence: |
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I1 LD R1, ALPHA
I2 MPY R1, R2, R3
I3 ST BETA, R1
I4 LD R1, GAMMA
I5 ADD R4, R1, R5. |
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