Each time one of these units is accessed or employed, an instruction execution event occurs, which occupies one or more cycles.
Simple machines implement instruction execution serially one instruction at a time. Further, they serially use the functional units that the machine comprises. We call machines that serially execute instructions using functional units as defined by the instruction set well-mapped machines. The process of instruction execution for such machines usually consists of the following events and sub-events (assuming R/M machine):
Instruction Fetch
Generate a real instruction address from the value stored in the PC.
Access the cache.
Access memory if a cache miss occurs.
Move the word fetched from the cache/memory (in the SR) to the IR.
Instruction Decode
Determine instruction type and addressing modes.
Fetch register operands.
Data Fetch
Generate a real data address from the offset in the instruction plus base and/or index values.
Access the cache.
Access memory if a cache miss occurs.
Execute
Use ALU to operate on SR and other specified register.
Update Registers
Adjust PC to point to the next instruction.
Store result of ALU operation in register.
Of course, many other events also might happen, but usually do not. All this is best understood by some examples.
