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the particular segment identified by the virtual address. It also indicates whether this segment is currently active in memory, and perhaps indicates certain communications and other rights belonging to this user segment. There are 28 = 256 4,096-byte pages that are possible in the particular segment selected. Only a certain number of these are active at any one time. The segment table base plus the 8-bit page offset of a page within a segment defines an entry into the page table associated with that particular segment. The page table defines whether or not that particular page is in memory at this time, and also produces the location in memory of that particular page. The output of the page table (12 bits in the case of the example in Figure 1.24) completes the address translation as long as both segment table and page table indicate valid entries. As a simple example, suppose a certain system has a segment table base located in (real) memory at the 32b address (in hex) 00100000, and suppose a particular user is allocated segments starting at 00000012. This is the user ID. |
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Now suppose that user produces a virtual address (in hex) of 15010AAB. Now (real) location 00100012 + 150 = 00100162 is accessed. Suppose it produces: |
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Page Table Base: 00A00111. |
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Now (real) location 00A00111 + 10 = 00A00121 is accessed, and it contains 00000BBB. The leading 5 (hex) digits are ignored, so that the final real address is BBBAAB (a 24-bit address). Note that the segment table base and the page table base are assumed to be real (24-bit) addresses. The upper two hex digits are ignored. |
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The overall process of accessing the user ID, segment table, and page table, plus performing the appropriate additions of index values, is a time-consuming processfrequently on the order of 2030 cycles. The TLB is the bypass that takes virtual page information, virtual segment information, and user ID information, while also accessing a small associative memory (or set-associative memory). If an entry is found, the process of accessing the segment table and page table is not required. Rather, the translation has already been completed at some prior time and the real address bits can be replaced in the physical address from the table lookaside buffer. Accessing the TLB is equal to or less than a single machine cycle. |
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1.8 Basic Instruction Timing |
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In this section, we discuss what happens and when during instruction execution. For simple machines, once an instruction set has been defined and the basic functional units determined, the interaction, execution sequence, and timing can be studied. |
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Functional units usually include: |
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Memory (including buffering and access units). |
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